`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:00:34 12/12/2008 
// Design Name: 
// Module Name:    TestRAM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TestRAM(
    input writeEnable,
	 input clock,
    input Enable,
	 input Enable2,
    input [15:0] writeData,
    input [15:0] memAddress,
	 input [15:0] vgaAddress,
	 output reg [15:0] memData,
	 output reg [15:0] vgaData
    );
	parameter RAM_WIDTH = 16;
	parameter RAM_ADDR_BITS = 12;

  reg [RAM_WIDTH-1:0] CR_RAM [(2**RAM_ADDR_BITS)-1:0];
  
//  The following code is only necessary if you wish to initialize the RAM
//  contents via an external file (use $readmemb for binary data)
  initial
$readmemh("main.dat", CR_RAM, 12'd0, 12'd4095);

  always @(posedge clock) 
  begin
	if(Enable)
	begin
     if (writeEnable)
        CR_RAM[memAddress] <= writeData;
     memData <= CR_RAM[memAddress];
	end
	
	if(Enable2)
	begin
		vgaData <= CR_RAM[vgaAddress];
	end
  end

endmodule
